Contact resistance in 90 nm CMOS technology and beyond has a significant impact on the device performance of small precision passive elements typically used for forming analog circuitry in CMOS circuits, which include, but are not limited to: buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas. Generally, higher contact resistance causes reduced device operation speed, increased device heating, and other undesirable consequences.
One approach to reduce the contact resistance is to increase the dopant concentration of the semiconductor device region to which the contact is to be made. The semiconductor device region, typically formed of a silicon or polysilicon layer, can be doped with impurities such as arsenic, phosphorus, boron, and the like. However, silicon or polysilicon has limited impurity solubility, and the ability to decrease contact resistance by increasing the dopant concentration is therefore limited, because it cannot proceed beyond the impurity solubility limits of the silicon or polysilicon. Further, high impurity concentration may adversely impact other device characteristics.
As the trend toward smaller device geometries proceeds, coupled with the desire for still further improved device performance, there is a continuing need for passive element structures and methods of forming same, which will allow further decreased contact resistance, especially for passive elements to be incorporated into 90 nm CMOS circuits.